Conventionally, an input clock signal is provided to a phase lock loop (“PLL”) for locking to such input clock signal to provide an output clock signal. However, as data rates have increased, such as a gigabit per second or more for example for serial links, phase noise associated with the input clock signal is more of a problem.
Accordingly, it would be desirable and useful to address phase noise in a clock signal. More particularly, it would be both desirable and useful to address phase noise in a clock signal for serial links having at least a gigabit-per-second bit rate.